The critical dimension (CD) of integrated circuits has decreased to sub-wavelength conditions for optical lithography, wherein the critical dimension of integrated circuits is close to or smaller than the exposure wavelength. Under these sub-wavelength conditions, wafer pattern distortion caused by lithographic process variations, such as lens aberration, misalignment, defocus, overexposure, optical diffraction, and polarization, have an impact on reliability and performance due to line-end shortening, corner-rounding, and line-edge roughness of integrated circuit patterns. To overcome the deficiencies of proximity effect distortion, resolution enhancement techniques may be utilized. However, in some instances, the manufacturing of nanometer transistor devices may be subjected to serious gate shape pattern distortion. Some electrical characteristics of transistor devices, such as threshold voltage and leakage current, may be seriously affected by sub-wavelength gate sizes and shapes. Current device models adopted by SPICE simulators cannot incorporate non-rectangular pattern distortion partly because threshold voltage and leakage current have complex nonlinear relationship with gate shape.
Thus, there exists a need to improve device models to account for sub-wavelength lithographic distortion.